Of late, semiconductor integrated circuits are being scaled down while attempts are being made to speed up operation of the circuits semiconductor devices.
Speeding up semiconductor devices can be achieved by in two ways, one being to cause each of the individual semiconductor devices to operate quickly and the other being to of use higher current through the circuit. However use of higher current in a semiconductor integrated circuit is likely to lead to unwanted transistor saturation and the generation of heat. A result of these drawbacks to the use of higher current is a reduction in chip lifetime. Therefore, these are limitations to the level of current which can be used in semiconductor integrated circuits and, accordingly, the majority of the efforts for realizing faster device operation are toward speeding up the operation of individual devices of the semiconductor integrated circuit. There is, thus, a great demand for novel semiconductor devices which can operate quickly.
Additionally, device isolation for bipolar semiconductor devices is in most cases implemented by the formation of pn junctions, although oxide isolation methods are also used in limited quarters of the semiconductor industry. The oxide isolation methods use silicon oxide layers formed around the bipolar semiconductor devices. None of these attempts has successfully led to the development of a semiconductor device in which a silicon oxide layer extends to the bottom of the substrate. Examples of silicon oxide isolated bipolar semiconductor devices are described by Tetsu Fukano et al, in his publication "Ultra Steep Grooves Formed by Peripheral Etching and Application to Device Isolation" (Semiconductor Integrated Circuit Symp., December 1982). In one of the processes disclosed in this publication, molybdenum silicide (MoSi.sub.2) is magnetron sputtered directly onto the surface of a silicon substrate to a thickness of about 0.3 microns. A patterned photoresist film (AZ-1350J) is placed on the resultant molybdenum silicide layer, which is then dry etched with a mixture of tetrachloromethane (CCl.sub.4) and oxygen gases to form grooves in the molybdenum silicide layer and the underlying silicon substrate along the edges of the photoresist pattern. Upon removal of the photoresist film and the remnant molybdenum silicide layer from the silicon substrate, a silicon oxide layer is formed by thermal oxidation of the silicon substrate. Grooves which are thus formed in the silicon substrate by the "peripheral etching" technique terminate halfway into the bulk of the silicon substrate. As a result the individual regions separated by the silicon oxide layers formed in the peripheral etched grooves in the silicon substrate can not be reliably isolated from one another.
If the grooves in the silicon substrate are to be formed so as to extend to the bottom of the silicon substrate, so that the semiconductor devices to be formed in the regions defined by such grooves can be effectively isolated by the silicon oxide layers in the grooves, the individual semiconductor devices must be formed to protrude from the surface of the substrate in order to enable the bulk silicon to be oxidated toward the bottom of the substrate. The presence of such protrusions on the surface of the silicon results in the formation of steps in the metallic wiring layer which might cause the wiring layer to break at the steps during the processing which takes place after device fabrication.
For this reason conventional bipolar transistors have been isolated in using a pn junction between the device and the p-type silicon substrate. A problem with this technique is that a parasitic capacitance is created at the interface between the substrate and the collector of the device which makes it difficult to speed up device operation. It may also be mentioned that a channel stop region must be provided between neighboring device regions isolated according to the conventional technique. Provision of such additional regions on the substrate significantly limits integration density.
It is, accordingly, an important object of the present invention to provide an improved semiconductor device which can be effectively isolated by silicon oxide without impairing the performance quality of the device while providing a significantly reduced parasitic capacitance and a significantly increased isolation voltage.
It is another important object of the present invention to provide an improved isolated semiconductor device in a densely integrated integrated circuit structure.
It is still another important object of the present invention to provide an improved semiconductor device with internal wiring easily implemented.
It is still another important object of the present invention to provide an improved semiconductor device which can be easily handled during processing which takes place after fabrication of the semiconductor device.
It is, yet, still another important object of the present invention to provide a method of fabricating such an improved semiconductor device according to the present invention.